Private company

Nantero

Novel computer memory type

Nano-RAM is a proprietary computer memory technology from the company Nantero. It is a type of nonvolatile random-access memory based on the position of carbon nanotubes deposited on a chip-like substrate. In theory, the small size of the nanotubes allows for very high density memories.2 Wikipedia text CC BY-SA 4.0

Last updated Oct 21, 2026.

Overview

2000Founded1

Nano-RAM is a proprietary computer memory technology from the company Nantero. It is a type of nonvolatile random-access memory based on the position of carbon nanotubes deposited on a chip-like substrate. In theory, the small size of the nanotubes allows for very high density memories. Nantero also refers to it as NRAM.2

The story

Nantero was founded in 2001, and headquartered in Woburn, Massachusetts. Due to the massive investment in flash semiconductor fabrication plants, no alternative memory has replaced flash in the marketplace, despite predictions as early as 2003 of the impending speed and density of NRAM.

In 2005, NRAM was promoted as universal memory, and Nantero predicted it would be in production by the end of 2006.

In August 2008, Lockheed Martin acquired an exclusive license for government applications of Nantero's intellectual property.

By early 2009, Nantero had 30 US patents and 47 employees, but was still in the engineering phase. In May 2009, a radiation-resistant version of NRAM was tested on the STS-125 mission of the US Space Shuttle Atlantis.

The company was quiet until another round of funding and collaboration with the Belgian research center imec was announced in November 2012.

Nantero raised a total of over $42 million through the November 2012 series D round.

Investors included Charles River Ventures, Draper Fisher Jurvetson, Globespan Capital Partners, Stata Venture Partners and Harris & Harris Group.

In May 2013, Nantero completed series D with an investment by Schlumberger.

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EE Times listed Nantero as one of "10 top startups to watch in 2013".

31 Aug 2016: Two Fujitsu semiconductor businesses are licensing Nantero NRAM technology with joint Nantero–Fujitsu development to produce chips, announced in 2018. They are announced to have several thousand times faster rewrites and many thousands of times more rewrite cycles than embedded flash memory. As of 2024, these products are still announced but have not reached the market.

In mid-to-late 2024, Nantero had ceased operations. Its website had been parked and some of its equipment was sold off by auction by August of 2024.

From Wikipedia’s article on Nantero, shared under CC BY-SA 4.0.3

Products and brands

The first generation Nantero NRAM technology was based on a three-terminal semiconductor device where a third terminal is used to switch the memory cell between memory states. The second generation NRAM technology is based on a two-terminal memory cell. The two-terminal cell has advantages such as a smaller cell size, better scalability to sub-20 nm nodes (see semiconductor device fabrication), and the ability to passivate the memory cell during fabrication.

In a non-woven fabric matrix of carbon nanotubes (CNTs), crossed nanotubes can either be touching or slightly separated depending on their position. When touching, the carbon nanotubes are held together by Van der Waals forces. Each NRAM "cell" consists of an interlinked network of CNTs located between two electrodes as illustrated in Figure 1. The CNT fabric is located between two metal electrodes, which is defined and etched by photolithography, and forms the NRAM cell.

The NRAM acts as a resistive non-volatile random-access memory (RAM) and can be placed in two or more resistive modes depending on the resistive state of the CNT fabric. When the CNTs are not in contact the resistance state of the fabric is high and represents an "off" or "0" state. When the CNTs are brought into contact, the resistance state of the fabric is low and represents an "on" or "1" state. NRAM acts as a memory because the two resistive states are very stable. In the 0 state, the CNTs (or a portion of them) are not in contact and remain in a separated state due to the stiffness of the CNTs resulting in a high resistance or low current measurement state between the top and bottom electrodes. In the 1 state, the CNTs (or a portion of them) are in contact and remain contacted due to Van der Waals forces between the CNTs, resulting in a low resistance or high current measurement state between the top and bottom electrodes. Note that other sources of resistance such as contact resistance between electrode and CNT can be significant and also need to be considered.

To switch the NRAM between states, a small voltage greater than the read voltage is applied between top and bottom electrodes. If the NRAM is in the 0 state, the voltage applied will cause an electrostatic attraction between the CNTs close to each other causing a SET operation. After the applied voltage is removed, the CNTs remain in a 1 or low resistance state due to physical adhesion (Van der Waals force) with an activation energy (Ea) of approximately 5eV. If the NRAM cell is in the 1 state, applying a voltage greater than the read voltage will generate CNT phonon excitations with sufficient energy to separate the CNT junctions. This is the phonon driven RESET operation. The CNTs remain in the OFF or high resistance state due to the high mechanical stiffness (Young's Modulus 1 TPa) with an activation energy (Ea) much greater than 5 eV. Figure 2 illustrates both states of an individual pair of CNTs involved in the switch operation. Due to the high activation energy (> 5eV) required for switching between states, the NRAM switch resists outside interference like radiation and operating temperature that can erase or flip conventional memories like DRAM.

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NRAMs are fabricated by depositing a uniform layer of CNTs onto a prefabricated array of drivers such as transistors as shown in Figure 1. The bottom electrode of the NRAM cell is in contact with the underlying via (electronics) connecting the cell to the driver. The bottom electrode may be fabricated as part of the underlying via or it may be fabricated simultaneously with the NRAM cell, when the cell is photolithographically defined and etched. Before the cell is photolithographically defined and etched, the top electrode is deposited as a metal film onto the CNT layer so that the top metal electrode is patterned and etched during the definition of the NRAM cell. Following the dielectric passivation and fill of the array, the top metal electrode is exposed by etching back the overlying dielectric using a smoothing process such as chemical-mechanical planarization. With the top electrode exposed, the next level of metal wiring interconnect is fabricated to complete the NRAM array. Figure 3 illustrates one circuit method to select a single cell for writing and reading. Using a cross-grid interconnect arrangement, the NRAM and driver, (the cell), forms a memory array similar to other memory arrays. A single cell can be selected by applying the proper voltages to the word line (WL), bit line (BL), and select lines (SL) without disturbing the other cells in the array. Alternatively between the bottom electrode and top metal layer they may be two layers of CNTs: one with uniformly arranged CNTs, and another with randomly arranged CNTs. The uniformly arranged CNTs are used to protect the randomly arranged CNTs from the top metal layer.

From Wikipedia’s article on Nantero, shared under CC BY-SA 4.0.3

Timeline

  1. 2000Founded Founded in Woburn1

Sources

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